1. Field of the Invention
This invention relates to a processor containing a reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal and a method for avoiding a bug therein.
2. Description of the Prior Art
In recent years, a style of processing data successively according to processor instructions written by software using a microprocessor has been a main stream in today's information processing apparatuses. The style of using the microprocessor has remarkable advantages in that the function can be changed by changing a software program, a plurality of functions can be achieved by the same hardware and the like. As an importance thereof has increased, the processor is required to carry out processing at further higher speeds.
FIG. 1 is a block diagram showing a structure of major parts of a conventional processor.
In this processor 100, an instruction is inputted through a data bus 101a and stored in an instruction cache 101. If a predetermined instruction is read from this instruction cache 101, it is sent to an instruction decoder 102 through a bus OP and decoded there, so that a control signal is generated in bus CS. Each circuit block and bus in the processor are controlled by this control signal.
Data processing is carried out by arithmetic operation between a register file 103 for storing source data necessary for the operation and function units (FU) 104-106. Data of the register file 103 is supplied to the function units 104-106 through bus RFD and a result of the operation is written back to the register file 103 through the bus 108. Data of the register file 103 is loaded and stored in the data cache 107 and vice versa.
FIG. 2 is a circuit diagram showing an example of a structure of the instruction decoder 102 of FIG. 1.
An instruction array (instruction vector) consisting of two values "0" and "1" sent through the bus OP is inputted to an instruction decoder 102 containing a gate circuit and as a result, various kinds of control signals CS are outputted. As shown in FIG. 2, the various kinds of control signals CS include a RegDst signal, ALUSrc signal, MemtoReg signal, RegWrite signal, MemRead signal, MemWrite signal, Branch signal, ALUOp1 signal, ALUOp2 signal and the like.
Here, the RegDst signal is a control signal for writing back to the register file 103. The ALUSrc signal is a source data control signal to be sent to the function units 104-106. The MemtoReg signal is a control signal for loading from the data cache 107 to the register file 103. The Regwrite signal is a control signal for writing to the register file 103. The MemRead signal is a control signal for reading to the data cache 107. The MemWrite signal is a control signal for writing to the data cache 107. The Branch signal is a control signal for branching. The ALUOp1 signal and ALUOp2 signal are control signals for the function units 104-106.
Higher speed of the microprocessor processing performance of this kind can be attained by only increasing the speed of synchronous clock inputted and increasing the number of instructions to be processed per clock cycle. Here, the latter has been attained by increasing a degree of parallelism of processing in parallel or the number of the function units (FU) which operate in parallel.
Increasing the speed by this method increases the number of the function units and the number of the control circuits, so that this increase of the number of the control circuits makes it very difficult to verify faults (bugs) in design of the microprocessor. Thus, because a complete verification for the processor is impossible in fact, usually latent bugs exist in most processors. Thus, there has been a demand for a skill for avoiding the bug.
In a conventional processor, as evident from FIG. 2, the respective circuits are fixed, so that a particular control signal is always generated to a particular instruction vector. In such a processor, if bugs exist in its function units and it has been made evident that a bug occurs under a particular instruction or particular operating condition, there is no way for avoiding the bug but replacing the processor with a processor containing no bug or determining conditions in software by rewriting all application software. If this is processed by software, there is a possibility that the processing speed may decrease significantly.
In the aforementioned conventional processor, although avoidance of the latent bugs on site can be achieved by rewriting application software for use, this is really impossible if what application software a user will use is not known. That is, according to the prior art, there is no microprocessor capable of identifying and correcting the bugs on site.